Due to the ever-growing density with which data must be stored on hard disks or similar magnetic media, it is useful, during the write phase of the data, to delay a transition, i.e. the switching of a bit from a low state to a high state or vice-versa, when in the immediately preceding clock phase there has been a transition in the opposite direction. This approach serves to compensate the shift of the physical position of the second transition towards the preceding transition already recorded on the hard disk. This anticipation (during a reading phase) of the second transition is mainly due to the so-called nonlinear intersymbol interference caused by the presence of a demagnetizing field produced by an immediately preceding transition, as well as by the partial data deletion in the transition zone due to the high density of data stored on the hard disk.
To implement this pre-compensation, i.e. to delay the transitions that immediately follow another transition, special circuitry is used comprising a delay circuit and a multiplexer to switch from the system clock to a slightly delayed clock to delay the output data stream. This switching is effected by a signal generated by a control circuit that identifies two transitions intervening in the input data stream as consecutive transitions.
Due to the generally high system clock frequencies, this type of approach has several drawbacks. A first drawback is that to operate at the system clock frequency, the delay circuit and the control circuit must be realized in ECL technology (Emitter Coupled Logic), with a consequent increase in the complexity and costs of the fabrication process compared to a typically preferred fully CMOS technology (Complementary Metal Oxide Semiconductor). A further drawback is that the multiplexer, operating at a high frequency, generates glitches that reduce the reliability of the device itself. Moreover, the delay circuit may delay the system clock for up to a half period, because greater delays would imply a write error at the instant of the switching from the delayed clock back to the system clock.